Putting The Alligator In The Matchbox

A Holistic View For Suppliers To The Semiconductor Industry

Guest Author: Jack Kessler
Long time member of the semiconductor equipment and materials community

A story goes that a man went to an old sage at the top of a mountain and showed him a picture of an alligator attacking a calf to show the relative size and ferocity of the animal. The man informed the sage that he would like to know the best way to catch an alligator without doing it or him harm. The sage closed his eyes and thought and presently asked if the man could easily obtain a matchbox, a pair of tweezers and a telescope. The man replied, "Of course but what has that to do with my catching an alligator?" The sage sighed and looked down at the bewildered man and explained, "Take the matchbox and open it and place the box and the tweezers on the ground in front of you. Now take the telescope and turn it, big end around, towards your eye. Now, focusing on the alligator, pick up the tweezers, grasp the alligator and place it in the matchbox and close the box."

It seems that many of us are trying to put the alligator in the box in the same manner by looking at our problem from the myopic view of a telescope turned wrong way 'round. We tend to focus on one small segment of the entire industry and put it all out of proportion to reality. If we work in wafer Fab, then wafer production is our alligator, and assembly and test have their own alligators in packaging and testing and sales has the biggest alligator of all, the customer. But it is way past time to put away our telescopes and put down our tweezers and matchbox and face reality.

As the density and complexity of wafer fabrication and die continues to increase as size decreases, we see packaging following the same trends of smaller and finer pitch and shrinking size and increasing complexity. In fact what some of us are witnessing is a congruence of technology where assembly processes are more easily integrated into wafer Fab than left in assembly. Examples that are being addressed today are KGD, flip chip and Wafer Scale CSP and only our imaginations can tell us where we will be in and what packages will look like even 5 years from now.

But from your view with your telescope you ask, "What has that to do with me, I am not building or selling any of those packages?" And in answer, I suggest that you look at the problems that the old and new package designs are creating in handling of parts for testing and taping. The high cost of test has long been attributed solely to test. However, many of us share the blame, from reduced die size and pad pitch forcing more expensive probe mechanisms, to packages with no identifying mechanical features for alignment, to packages wider than they are long, to packages with leads on all four sides to random size Chip Scale packages sawn to shape. It is no secret that many of the new packages are delayed in their introduction and acceptance because we did not plan for either handling, testing or taping until we were forced to.

What if we were to take an overall view and assume a responsibility for the entire process? How much money, resources and time could be saved if we put aside our telescopes and viewed the entire process of designing, Fabbing, assembling, testing, taping and placing semiconductors as a single integrated process? If we go out and sell a totally new product or process and only include the parts of the process that we are involved in, will the customer be able to use it or even be interested? Doubtfully, yet that is exactly what each and everyone of us has been and is doing, viewing the world from the wrong end of the scope. I am not suggesting that you or your company take or have responsibility for an entire process, but being more closely aware of how each part fits and affects the processes both before and after our specialty is not unreasonable, relatively unknown today, but not unreasonable.

Hopefully, with this awareness would come the responsibility to make the best possible overall decision on design and form as well as function. This means that you would need to communicate and discuss with and share common solutions with the other technologies. The goal being to make certain that your design change or new technology has minimum impact on the processes that follow or precede it and to discuss how best to accommodate it into the overall picture. It is no secret that you can have the best design in the world, but if it cannot be tested or handled, it is of no value to anyone but you, yet the process continues to occur, in spite of the obvious, due to our tunnel vision.

Is looking at and working within the guidelines of the overall process an unreasonable approach and just a pipe dream? Well according to a discussion with Wayne J. Howell Ph. D. Senior Technical Staff, IBM, VT, during the recent MEPTEC conference on SOI and Si Ge (1), that is exactly the process being done at his division at IBM. New processes and technology are viewed in their entirety by all divisions to ensure that a new project is technically and financially feasible from start to finish. Open lines of communication are made available to share possible impacts and solutions as the project goes from design to silicon to plastic to PCB.

And on a smaller scale, in a recent article in Chip Scale Review, by packaging and test engineers from National Semiconductor, titled "Integrated Assembly and Strip Test of Chip-Scale Packages" (2) , the point was made more than once, that packaging designers must be aware of strip testing requirements. Mainly the need to isolate pads (leads) prior to test to allow massive parallel testing in lead-frame and strip formats. Testing in a strip format allows the user to greatly reduce test costs and time to market yet it may actually cost the assembly division some small amount to add this step to the process. But the overall savings is tremendous and cannot be ignored to save the cost of one process step normally done in PCB manufacture, removing the plating/shorting bars. As we move forward with finer line geometry, smaller die, more complex circuits requiring more and longer testing, faster time to market, higher frequencies demanding less interface between the die and finished product we move will be forced to move towards a more consolidated process. It is not unreasonable to project that some OEM's or even large sub-contractors will consolidate wafer Fab, assembly and test into one process and one division for low ASP high volume products like RAM packaged in Wafer Scale CSP packages and others. The need to reduce costs will demand a reduction in redundant processes and equipment, unlike the present placement of multiple quarter to half million dollar lead inspection systems now purchased for assembly, test and taping operations.

So where are you and your company? Still buying more telescopes and matchboxes? Or are you one of the exceptional companies that realize that there are more efficient overall means to do things to ensure the success of the final product, and still keep your costs in line and actually reduce them? And are you supporting your customer by ensuring the product format that you sell will not bury your customer while he is trying to find a way to use, test or place what he bought?


1. MEPTEC March 8, 2000, "The Material, Packaging and Manufacturing
Challenges of SOI and Silicon Germanium".
2. "Integrated Assembly and Strip Test of Chip-Scale Packages" Chip Scale
Review, March/April, 2000

About the author

Jack Kessler, is the owner of the "Assembly through Tape" consulting firm, Concepts Unlimited, and has been in the semiconductor industry for over 25 years. Prior to forming Concepts Unlimited, he worked for NSC for 15 years and Amkor Technology for 10. He was instrumental in introducing the first pick and place handler to the US in the mid '80's and most recently in bringing strip based testing technology and processes to the attention of the industry. As a member of SEMI and MEPTEC committees he is active in promoting new technologies and directions for the entire industry. His articles on testing both conventional as well as "in-strip" have been published in Chip Scale Review (May '98, March/April, '99Sept/Oct, '99), Future Fab (volumes 5, 7, 1999 & volume 8, 2000), MEPTEC Report, (Jan/Feb, 2000, Mar/April, 2000). He may be reached at jkess@msn.com or at 408-725-8698.